how to force data in design instead of using testbench

hi guys i was wondering if there is a way to force bit in a design instead of using testbench? like verilog code for single port ram below how to force ram[address] into 1000 instead of using testbench?

module RAM(clk, rst, w, r, data, address, read, read_out);
parameter length = 4;
parameter depth = 8;
input clk, rst, r, w;
input [length-1:0] data, address;
output [length-1:0] read;
output reg[length-1:0] read_out;
reg[length-1:0] ram [depth-1:0];
assign read = ram[address];

always@(posedge clk) begin
if (!rst) begin
    ram[address] <= data;
    else if (r)
    read_out <= ram[address];
else begin
    if (w)
    ram[address] <= data;


There is a procedural continuous assignment type of statements that have precedence over any procedural statements. These are assign statements inside always block.

Referring to example in SystemVerilog LRM 1800-2012 Section 10.6,

The assign procedural continuous assignment statement shall override all procedural assignments to a variable. The deassign procedural statement shall end a procedural continuous assignment to a variable.

The value of the variable shall remain the same until the variable is assigned a new value through a procedural assignment or a procedural continuous assignment.

So, you can have a combinational always block to override the existing value:

module ram...
//... Some logic 
assign ram[address] = whatever_data
// assign ram[address] = 'h1000;
deassign ram[address];

always@ (posedge clk, negedge reset)
// No change here.


A new continuous assignment process is created when the line is reached in the procedural block.

assign can be applied to all the types like reg, integer etc but not on nets (force must be used for nets).

Moreover, procedural continuous assignments are synthesizable.

However, they can easily be misused and hence they must be used sparingly. A better alternative is to find out some other driving logic.

For more information, refer to this and this links. While, procedural continuous assignment can be found out at SystemVerilog LRM IEEE 1800-2012 section 10.6.


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