uvm monitor methodology & run_phase

I'm wondering if I have a miss understanding about the uvm methodology of the monitor run_phase task. The DUT sends out multiple clocks with data that the monitor is watching and checking, keeping the different clock domains separate. So my run phase task looks like

forever begin
begin @(posedge clk1) begin
..code to capture data..
end end
begin @(posedge clk2) begin
..code to capture data in this domain...
end end
disable fork;

My 'problem' is if clk1 and clk2 are aligned then only one of the posedge statements gets executed. Additionally if I want my monitor to perform some other operations on a third async domain say, at a multiple of clk1 or clk2 then there is a problem when the third domain lines up with clk1 or clk2.

How is the monitor suppose to work in multiple clock domains in its run phase forever loop?


Usually when monitoring two different clock domains they are kept as separate forever-loop threads. There code be cases you want want to disable the other but I don't think that is what you intend.

  forever @(posedge clk1) begin
    ..code to capture data..
  forever @(posedge clk2) begin
    ..code to capture data in this domain...
join // or join_non


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