uvm monitor methodology & run_phase

I'm wondering if I have a miss understanding about the uvm methodology of the monitor run_phase task. The DUT sends out multiple clocks with data that the monitor is watching and checking, keeping the different clock domains separate. So my run phase task looks like

forever begin
fork
begin @(posedge clk1) begin
..code to capture data..
end end
begin @(posedge clk2) begin
..code to capture data in this domain...
end end
join_any
disable fork;

My 'problem' is if clk1 and clk2 are aligned then only one of the posedge statements gets executed. Additionally if I want my monitor to perform some other operations on a third async domain say, at a multiple of clk1 or clk2 then there is a problem when the third domain lines up with clk1 or clk2.

How is the monitor suppose to work in multiple clock domains in its run phase forever loop?


ANSWERS:


Usually when monitoring two different clock domains they are kept as separate forever-loop threads. There code be cases you want want to disable the other but I don't think that is what you intend.

fork
  forever @(posedge clk1) begin
    ..code to capture data..
  end
  forever @(posedge clk2) begin
    ..code to capture data in this domain...
  end
join // or join_non


 MORE:


 ? Coverage done by monitor or subscriber in UVM
 ? Difference between two Specman events with the same sampling event @sim
 ? UVM -Create my own macros
 ? Is there a specific way to stop the test/simulation in case condition failure?
 ? How can you add systemverilog class variables or class members to waveform?
 ? The different between factory, config_dg, and resources_db
 ? can anyone please suggest me s free simulator for practicing UVM and systemverilog for windows 10 OS?
 ? How to Dump a UVM TB class diagram?
 ? UVM-SystemC compiling and linking using Eclipse and Cygwin
 ? SystemVerilog- How to write a constructor with initialization?