I'm wondering if I have a miss understanding about the uvm methodology of the monitor run_phase task. The DUT sends out multiple clocks with data that the monitor is watching and checking, keeping the different clock domains separate. So my run phase task looks like
forever begin fork begin @(posedge clk1) begin ..code to capture data.. end end begin @(posedge clk2) begin ..code to capture data in this domain... end end join_any disable fork;
My 'problem' is if clk1 and clk2 are aligned then only one of the posedge statements gets executed. Additionally if I want my monitor to perform some other operations on a third async domain say, at a multiple of clk1 or clk2 then there is a problem when the third domain lines up with clk1 or clk2.
How is the monitor suppose to work in multiple clock domains in its run phase forever loop?