? ADT7420 Temperature reading -Verilog

I have the following code to try and read the ADT7420 on my nexys4DDR FPGA board. I can't seem to get it to work. All of the led's wind up set to on, and I can't find the problem. Where am I going
 ? Priority encoder in verilog

I am somewhat new to verilog, I tried running this code but it gives me an error:module enc(in,out); input [7:0] in; output [3:0] out; reg i; reg [3:0] out; always @* begin for (i=0;i<
 ? Arithmetic Right Shift in Verilog

As part of a processor design, I am implementing a simple behavioral right shifter using Verilog.The shifter inputs a 32 bit variable and outputs either a right logical shift or a right arithmetic shi
 ? FPGA interface protocol

I am looking for a very fast protocol to implement interface communication between FPGAs (at the moment I am using emulated Virtex-7 FPGA). Actually my requirements for the project I work on are reall
 ? How to do linting with Questasim?

I was using linting tool HAL from Cadence. Now I have to use Questasim. But I don't know about the tools or switch that I can use for linting. Is there any tool from Mentor(Questaism) like HAL from Ca
 ? Verilog: I2C read operation

In a verilog simulation, I will have to communicate with the 64K I2C EEPROM from Microchip. Every time for getting an ack from slave, I am driving my SDA to high impedance for a given clock period. No
 ? How to assign the data bus with data more than the width in verilog

I have a data bus of width [127:0] which is 128 bits.I have data of [4095:0] which is 32769 bits .I want to send continuously this 4Kb data through data bus.How can I do this? I think you can ju
 ? Missing signal names in Lattice Diamond

I have a Lattice Diamond project for an SPI multiplexer, which has the following module definition:module spimux(input bmck,input bssel,input bmosi,output bmiso,input[3:0] a,output[13:0] mck,output[13
 ? Errors during synthesis

I had written a Verilog code given below for simulation purpose.It is working properly during simulation. module read_1(clk,reset); input clk,reset; reg [0:23]dataout; reg htpv; reg [0:23]e_data; reg[
 ? Kind stuck on the output when the output overlap

I am very new on verilog.So this is my question: Implement 16 bits ALU with 16 bit register. This project should meet the following requirement. 1. Design a 16 bitALU : Design a 16 bit ALU that X
 ? Can't fit settability in counter Verilog

I have written up/down counter and created code for settable starting point. So far so good but I can't think of how to add it to the counter. I have to highlight that I'm completely new to Verilog an
 ? Verilog - Delay in implementation of SPI master slave interface

My code for top module (spi master slave):module top(en,en_s,sclk,data_rg,tr_rg,rst,s_rst,ss_bar,rcv_rg,m_data_rg);input [7:0] data_rg,tr_rg;input en,en_s,sclk,rst,s_rst,ss_bar;output [7:0] rcv_rg,m_d
 ? SPI slave doesn't work when I follow the spec, does when I don't?

I wrote an SPI slave in Verilog. There are some implementations out there, but I am still learning Verilog and digital logic in general, and so I decided I'd try to write it on my own.My implementati
 ? SPI slave doesn't work when I follow the spec, does when I don't?

I wrote an SPI slave in Verilog. There are some implementations out there, but I am still learning Verilog and digital logic in general, and so I decided I'd try to write it on my own.My implementati
 ? SPI slave doesn't work when I follow the spec, does when I don't?

I wrote an SPI slave in Verilog. There are some implementations out there, but I am still learning Verilog and digital logic in general, and so I decided I'd try to write it on my own.My implementati
 ? What does <= operator do in this code?

module counter (clk,rst,enable,count);input clk, rst, enable;output [3:0] count;reg [3:0] count;always @ (posedge clk or posedge rst)if (rst) begin count <= 0;end else begin : COUNT while (enable

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